{"data":{"kind":"file","path":"README.md","version_id":"s3qpq7olyzbze3x64pt6vluj","entry":{"name":"README.md","path":"README.md","is_directory":false,"size":2601,"modified_at":"2026-10-20T10:10:58.505000","content_hash":"e8709da0327ec69afa194dddcfb9d74eed7fa0896712dc785ce92202f3f9b3e4"},"entries":[],"content":"# ChipFlow PPA V3 — Datapath Scheduling + Functional Repair\n\n**Role alignment:** Applied Research – Chip Design: simulation-grounded design decisions, hard engineering constraints and quantitative PPA feedback.\n\nThis package provides **two distinct challenges**, configured by `--env.taskset.challenge mixed|schedule|rtl`:\n\n1. **Schedule:** an agent sees a datapath DAG from four families and emits a resource schedule as JSON. The evaluator rejects dependency hazards, unit conflicts, memory-port contention, fabricated unit indexes and power/area/latency breaches.\n2. **RTL-like repair:** an agent sees a 4-bit faulty gate network and 16 input/output examples, then patches exactly one gate. The deterministic grader verifies the output for **all 4,096 combinations** of inputs `a`, `b`, `c`; no arbitrary candidate code executes.\n\n## Scoring\n\n- Hard gate: precedence, exclusive use of each physical unit, one access per memory bank per cycle, maximum 2 units of each type, cycle validity and PPA limits.\n- A feasible schedule starts at `0.45`.\n- Improvement terms: `0.30` for approach to DAG critical-path latency, `0.20` for saved unit area, `0.05` for lower peak power.\n- All metrics are analytically computed; there is no arbitrary submitted code execution and no judge model.\n\nFor RTL-like repair, fully equivalent output yields `1.0`. A non-equivalent but structurally valid patch gets no more than `0.25 × exhaustive_accuracy`. Invalid patch shapes, unknown operators and forward wire references receive zero. This partial signal cannot exceed a fully correct result.\n\nTaskset: `chipflow-ppa` (64 tasks by default, `mixed` alternates 32+32; configurable `num_cases`, `seed_start`, `challenge`). Scheduling uses a memory-port-aware greedy reference. The RTL reference patch is evaluator-only and must never be exposed to a solver. The 4-bit gate DSL is **not Verilog**, and the exhaustive checker is a correctness proof only within this restricted language.\n\n## Example output\n\n```json\n{\"schedule\": [{\"id\": \"n0\", \"start\": 0, \"unit\": 0}, {\"id\": \"n1\", \"start\": 0, \"unit\": 0}]}\n```\n\nThe example only illustrates scheduling syntax; a full schedule must list every operation. The RTL repair format is `{\"patch\":{\"id\":\"n4\",\"op\":\"xor\",\"args\":[\"n3\",\"b\"]}}`.\n\n## Scope and limitations\n\nThis environment models high-level chip datapath scheduling with transparent area/power proxies. It does **not** synthesize Verilog or measure transistor-level PPA. A production-grade extension should execute Icarus Verilog + formal equivalence + Yosys/OpenROAD in a verifier-only container with private tests.\n","encoding":"utf-8","truncated":false,"total_bytes":2601},"status":null}